1. Field of the Invention
The present invention relates generally to phase and frequency locked signal sources, and more particularly, to an improved frequency lock loop (FLL) incorporating a 1-port tunable frequency discriminator for reducing phase noise and settling times over prior art frequency locked loop circuits.
2. Description of Related Art
Signal sources for generating frequency coherent signals are useful in a number of applications, including use as a precise radio frequency reference signal source. Particularly useful for such frequency generation are electronic circuits known in the art as voltage controlled oscillators (VCOs). However, disadvantageous characteristics common to tunable signal sources, including VCOs, is that there is the presence of non-frequency coherent signal sidebands, commonly referred to as phase noise (PN). Another disadvantageous characteristic is that there is continued frequency drift after initially tuning the VCO to a desired frequency, known as post tuning drift (PTD).
High performance low phase noise signal sources in use today typically produce PN values of 75 dBc/Hz at 10 kHz and 104 dBc/Hz and 100 kHz from the VCO carrier frequency, and PTD values on the order of 4 MHz to 7 MHz, in a 1 microsecond time frame. To improve upon these performance characteristics, various frequency lock loops (FLLs), phase lock loops (PLLs), multiple loop PLLs (MLPLLs), direct synthesis synthesizers (DSS), and combinations of these circuits have been used to reduce unwanted PN and PTD. Unfortunately, there remain problems with performance, cost, and physical size, among others, when using these circuits.
PLL frequency synthesizers are the most common of the frequency lock loop circuits and have been utilized with VCO's for many years to provide a stable output signal having a precise and predictable frequency. The use and limitations of PLLs are well known in the art. Of particular concern with PLLs has been the problem of small frequency step size requirements, due to practical chip noise limitations and PN degradation. The PN degradation is 20* log (N), where N is the total divisor required to tune a VCO to a specific frequency. It follows that single loop synthesizers that have very small step size requirements particularly suffer in their PN performance, due to the necessarily large values of N.
Common prior art efforts to solve this problem have been to use DSS or MLPLL circuitry. However, both of these circuits are substantially expensive and require a significant amount of physical volume. Further, both of these techniques tend to generate unwanted spurious signal products. Another prior art technique for solving this problem is the utilization of an FLL in conjunction with a PLL. In this combination, the FLL accomplishes noise reductions, while the PLL accomplishes the phase lock and reference signal tracking. Typically, such FLLs use a 2-port delay line discriminator and a complex broadband voltage tunable delay line. Unfortunately, these circuits are also complex, costly, and substantially large in physical size.
Thus, there exists a need for an improved frequency lock loop (FLL) incorporating a 1-port tunable frequency discriminator for reducing phase noise and settling times over prior art frequency lock loop circuits.